The transition time, rise time or fall time, of an output driver is the time required for the output signal to slew between two voltages, typically 20% and 80% of full swing. In certain prior-art systems, for example, transition time must be maintained larger than a specified minimum value to keep the derivative of the supply current, and hence the inductive switching noise (sometimes called simultaneous switching output (SSO) noise), within limits. At the same time, transition time must be kept smaller than a maximum value to avoid excessive delay of the signal.
Across variations in process parameters, supply voltage, and temperature, transition time can vary by a considerable amount, often by a factor of two or more. In some applications, the spread between maximum and minimum values for transition time is wide enough so that this variation is acceptable. In other applications, however, the window of legal transition times is small and such a large variation in transition time is unacceptable.
Transition time control has been employed in prior art systems with relatively slow signaling rates, where the bit time is greater than 10 gate delays. At such data rates, transition time can be controlled by using a tapped delay line to sequence the stages of a segmented transmitter or by slowing the predriver stage of a transmitter. These techniques are discussed in Dally and Poulton, Digital Systems Engineering, Cambridge, pages 533–536.
Still other prior art systems have employed transition time control by controlling the transition time of a pre-driver which, in turn, controls the transition time of the output driver. The pre-driver transition time may be controlled by varying its supply voltage, controlling its supply current, or enabling a variable number of parallel pre-driver elements. As explained in Dally and Poulton, pp 533–536, slowing the transition time of the pre-driver in this manner can lead to severe inter-symbol interference, especially at high signaling rates. Because the output stage typically has significant gain, the predriver must be made very slow to give an output transition time that is a substantial fraction of a bit time. Often the pre-driver is so slow that it is not able to swing full-rail before the end of the bit time leading to significant inter-symbol interference due to the retained state.
In systems that operate at fast signaling rates, where the bit time is just a few loaded gate delays (less than 10), neither of these prior art transition control mechanisms is applicable. The transition time in such high-speed systems is just a few gate delays (less than 3) and thus comparable to the delay of a single tap of a tapped delay line. Because the entire transition must occur in just one (or at most two) taps of the delay line, it is not possible to smoothly sequence the transition by using a tapped delay line to sequence transmitter segments.
In such high-speed systems, the transition time is typically a large fraction of the bit time (usually 30%–50%). This is because a faster transition time would stress the bandwidth of the transmission medium (package, PC board, and connectors) without offering any substantial advantage. With such a ratio of transition time to bit time, it is not possible to control the transition time by slowing the predriver. To do so would require the predriver to have a delay much longer than the bit time and thus would cause intersymbol interference.
Because of these limitations, prior-art high-speed signaling systems have not employed transition time control and, as a result, have incurred large variations in transition time across process, voltage, and temperature corners.